1. Field of the Invention
The present invention relates generally to a solid state camera which picks up an object by displacing the image thereof and particularly to a solid state camera in which one or two image sensors are used to generate three primary color signals.
2. Description of the Prior Art
A prior art analog signal processing circuit for use with a CCD (charge-coupled device) camera having a plurality of picture sensing units, which employs a pick-up method by displaying an image by one-half of an alignment pitch of picture sensing units, is constructed as shown in FIG. 1. In this figure, reference numerals 1, 2 and 3 respectively show CCDs which generate R(red), B(blue) and G(green) signals of an object whose image is projected thereon through optical lenses L1, L2 and L3. These CCDs 1, 2 and 3 are respectively driven by a common drive clock with the frequency of 2 fsc (fsc is the frequency of a color sub-carrier) supplied thereto from a clock generator CKG through a terminal 4, and the CCDs 1 and 2 are displaced from the CCD 3 in the lateral direction at the pick-up position by one-half of the alignment pitch L of the picture sensing units. The outputs from these CCDs 1, 2 and 3 are respectively supplied to sample and holding circuits 5, 6 and 7. The sampled data corresponding to respective picture sensing units of the CCDs 1 and 2 are coincident with each other at spatial position as shown in FIG. 2A by R.sub.1, R.sub.3, R.sub.5, . . . and B.sub.1, B.sub.3, B.sub.5, . . . , while the sampled data of the CCD 3 are displaced by 1/2 alignment pitch of the picture sensing unit as shown by G.sub.2, G.sub.4, . . . also in FIG. 2A. However, since the CCD 1, 2 and 3 are driven by the common clock, the G signal derived from the CCD 3 is coincident with the R and B signals in timing as shown in FIG. 2B. Thus, the outputs from the CCDs 1 and 2 are respectively fed through the sample and holding circuits 5, 6 and low pass filters (post filters) 9, 10 with the band of, for example, 0.5 MHz to a matrix circuit 12, while the output from the CCD 3 is fed through the sample and holding circuit 7, a sample and holding circuit 8 and a low pass filter (post filter) 11 to the matrix circuit 12. FIG. 2C shows a sample pulse with the period of 1/2 fsc for the sample and holding circuits 5, 6 and 7, while FIG. 2D shows a sample pulse for the sample and holding circuit 8. By the latter sample pulse, the G signal is delayed by the period of 1/4 fsc corresponding to the 1/2 alignment pitch of the picture sensing units, made as the G signal corresponding to the picked-up position shown in FIG. 2E and then supplied to the matrix circuit 12. At output terminals 13, 14 and 15 led out from the matrix circuit 12 respectively obtained are a Y(luminance) signal and two color difference signals I and Q.
The color signals are processed as the analog signal set forth above and after passing through the low pass filters 9, 10 and 11 they are subjected to the matrix operation. Then, sampled outputs R.sub.2n+1 and B.sub.2n+1 of the R and B signals and a corresponding sampled output G.sub.2n+1 of the G signal are synthesized so that an error similar to misregistration is not caused. In other words, the component of G.sub.2n+1 is not read out from the CCD 3, but interpolated due to passing through the low pass filter 11 and then the sampled output corresponding to the G.sub.2n+1 is obtained from the low pass filter 11.
Now, such a case is considered that the outputs from the CCDs 1, 2 and 3 of the pick-up method where the image is displaced as mentioned above are sampled and then converted to digital data. FIG. 3A shows the sampling positions of the CCDs 1, 2 and 3 in which a symbol "X" represents a holding period (which is same in the following description and drawings). Further, in order to carry out a digital modulation represented by a circulating vector in which one color difference signal i.e. I signal and the other color difference signal i.e. Q signal alternately exist with the period of 1/4 fsc as shown in FIG. 4, 2 fsc is necessary as the respective data rate of the I and Q signals. To this end, the I signal is produced at timings of T.sub.1 and T.sub.3 in FIG. 3A and the Q signal is produced at timings T.sub.2 and T.sub.4 in FIG. 3A. In this case, since there is no G signal in the timings T.sub.1 and T.sub.3, by delaying the original G signal by 1/4 fsc, obtained are signals shown in FIG. 3B. Then, these signals and the original are synthesized to produce G signals shown in FIG. 3C, and then the G signals thus produced are used to provide the I signal shown in FIG. 3D. If the delay element is taken as EQU Z.sup.-1 (=exp{-(j.omega./4fsc)})
factors or coefficients, EQU I=r.multidot.R+b.multidot.B+g.multidot.G.multidot.Z.sup.-1
is established. In other words, an error similar to the misregistration of (1/4 fsc.apprxeq.70 n sec) is generated. This fact is entirely similar to the Q signal.